Conventionally, for synchronous transmission of data between LSIs, a transmitter-side LSI outputs a transfer clock to a receiver-side LSI along with the transfer data, and the receiver-side LSI reproduces the data by using the transfer clock. In a case where there is mutual transfer of data between the LSIs, different clocks are used for the transfer from a master LSI to a slave LSI and for the transfer from the slave LSI to the master LSI to achieve high-speed transfer. In this case, however, it is necessary to use a relatively complicated circuit device which includes a feedback loop for phase adjustment when the phase of the clock is adjusted on the receiver side. Further, since there is a difference in wiring delay of the LSIs between an evaluation board and an actual device or the like, there may generate a difference in timings on the entire system (between the LSIs) depending on the wiring delay. Such difference may generate a case where the entire system cannot be synchronized or a case where it is difficult to conduct the action timing verification equivalent to that of the actual device with bit precision and cycle precision.
Patent Document 1 depicts a phase detection circuit which separately samples input common data signals at a rise and a fall of a clock signal, and detects phases of the data signals and the clock signal based on the phase difference between the obtained two-system sampling signals. With such phase detection circuit, not only the phase shift generated constantly between the data signal and the clock signal but also the phase shift generated occasionally can be detected securely.
In the meantime, in order to synchronize the timings in the entire system, there is a method with which all the LSIs use a transfer clock that synchronizes with the same timing. Data transfer between the LSIs is achieved by exchanging the data in one cycle on the basis of the transfer clock. In this case, however, the frequency of the transfer clock depends on the wiring delay on the valuation board and the actual device, so that it is sometimes difficult to precisely estimate the wiring delay (load capacity) on both at a designing stage of LSI. Further, when the transfer clock frequency is aligned with the one with the larger wiring delay, the transfer throughput is deteriorated. Therefore, there are cases where the required performance cannot be achieved.
Patent Document 2 discloses a method which performs data transmission from a first LSI to a second LSI with synchronous transmission of 1.5-clock latency, and performs data transmission from the second LSI to the first LSI with synchronous transmission of 1.5-clock latency. This method makes it possible to guarantee the delay time of an input/output buffer including the clock skew between the LSIs and the flip-flop setup time both for the maximum time and minimum time.
In regards to this, Patent Document 3 depicts an information transmission device which can minimize the data delay time for a synchronous clock of a receiver, so that no limit is set in the number of slave devices connected with a small drive capacity even when a plurality of slave devices are connected to a single master device, and no limit is set in the frequency of a communication clock and path length of transmission path lines by the number of connected slave devices.
Patent Document 1: Japanese Unexamined Patent Publication H07-177134
Patent Document 2: Japanese Unexamined Patent Publication H08-249275
Patent Document 3: Japanese Unexamined Patent Publication 2001-265716